2026-06-10 –, Poster Island B
This paper presents the riscv-test-platform, an enhanced set of environments built upon the riscv-test-env, designed to facilitate the execution of tests and benchmarks on RISC-V architectures atop bare-metal environments. Their balance between code complexity and features make them a flexible platform to execute software in both simulated and FPGA environments, bridging the gap between the two platforms, with the advantages that each provide. The result is a set of four environments that mimic the functionalities of the original riscv-test-env, with the addition of some benchmarking features, which exercise more parts of RTL designs and help verification teams spot mismatches in the early stages of development.
This paper discusses riscv-test-platform, an extensible test environment collection designed to build versions of a single test routine in multiple target configurations. As mentioned in the abstract, the project is based on the riscv-test-env repository, and makes a case for extensible bare-metal environments that unify common differences in RISC-V designs. It also explores two cases in which it helped our verification team improve test coverage and bug reproducibility.
Computer Science and Engineering graduate and Master’s student in HPC, both at Universitat Politècnica de Catalunya. Working as a Junior Research Engineer at the Barcelona Supercomputing Center, developing solutions to advance verification of RISC-V designs.