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UID:pretalx-eu-summit-2026-3X9NJV@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T142000
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DESCRIPTION:The adoption of capability-based architectures such as Capabili
 ty Hardware Enhanced RISC Instructions (CHERI) in constrained RISC-V syste
 ms raises open questions regarding performance overheads\, verification co
 mplexity\, and practical evaluation methodologies. Virtual prototyping pro
 vides an effective means to explore these questions early in the design pr
 ocess\, before committing to Register-Transfer Level (RTL) implementations
 . In this paper\, we present a CHERI-enabled RISC-V Virtual Prototype (VP)
  targeting constrained embedded systems and demonstrate its use for early 
 architectural evaluation. We describe VP-based verification workflows for 
 both software and hardware and report early performance insights focusing 
 on CHERI tagged memory management. Our experiences highlight the benefits 
 of VPs for guiding CHERI adoption decisions and identify practical challen
 ges\, including the need for lightweight benchmarks suitable for constrain
 ed environments.
DTSTAMP:20260715T065845Z
LOCATION:Poster Island A
SUMMARY:CHERI-VP: Evaluating CHERI Early for Embedded RISC-V Systems with V
 irtual Prototypes - Spandan Das
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/3X9NJV/
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