FPGA fault injection (FFI) is a well-known technique for verification and robustness assessment of critical systems. However existing FFI tools for current generation FPGAs support only FPGA-specific fault models irrelevant for ASIC prototypes, and feature very coarse-grain analysis insufficient for localization of dependability bottlenecks in the design. To address these limitations have developed a bit-accurate FFI tool (BAFFI), capable of emulating ASIC (RTL) faults at the level of individual netlist cells. This paper explains how BAFFI can be used to obtain robustness estimates for RTL designs and exemplifies this through a case study of an open-source RISC-V SoC.