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UID:pretalx-eu-summit-2026-8ALWHG@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T155000
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DESCRIPTION:FREESS (Free Educational Superscalar Simulator) is an open-sour
 ce teaching environment for instruction-level parallelism in a RISC-V-insp
 ired superscalar processor. It provides a compact\, cycle-by-cycle view of
  register renaming\, issue\, execution\, write-back\, commit\, and memory 
 ordering in a Tomasulo-style machine. The simulator exposes the register m
 ap\, free pool\, instruction window\, reorder buffer\, and load/store queu
 es in one textual representation\, so the evolution of the hardware state 
 can be followed on screen and reproduced on paper. Runtime parameters such
  as issue width\, queue sizes\, and functional-unit latencies can be chang
 ed easily\, enabling direct comparison among alternative superscalar organ
 izations. The tool has supported Advanced Computer Architecture teaching f
 or about fifteen years and is publicly available on GitHub.
DTSTAMP:20260522T163501Z
LOCATION:Poster Island D
SUMMARY:FREESS: A Web-Based Educational Simulator for a RISC-V-Inspired Sup
 erscalar Processor Tomasulo-Style - Roberto Giorgi
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/8ALWHG/
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