2026-06-09 –, Poster Island D
FREESS (Free Educational Superscalar Simulator) is an open-source teaching environment for instruction-level parallelism in a RISC-V-inspired superscalar processor. It provides a compact, cycle-by-cycle view of register renaming, issue, execution, write-back, commit, and memory ordering in a Tomasulo-style machine. The simulator exposes the register map, free pool, instruction window, reorder buffer, and load/store queues in one textual representation, so the evolution of the hardware state can be followed on screen and reproduced on paper. Runtime parameters such as issue width, queue sizes, and functional-unit latencies can be changed easily, enabling direct comparison among alternative superscalar organizations. The tool has supported Advanced Computer Architecture teaching for about fifteen years and is publicly available on GitHub.
Educational Tool for SUPERSCALAR RISC-V teaching.
Available (and runnable) in GitHub or standalone in portable C.
Roberto Giorgi is an Associate Professor in the Department of Information Engineering at the University of Siena, Italy (qualified for Full Professorship). He received his PhD in Computer Engineering and his Master’s in Electronics Engineering, both summa cum laude, from the University of Pisa. He coordinated the 4-year TERAFLUX (Future and Emerging Technologies) and 3-year AXIOM (H2020) projects, was a Work Package leader in Embedded Reconfigurable Architecture, and contributed to HiPEAC and SARC. He participated in ChARM, developing software for ARM-based embedded system performance evaluation. Selected as an ICT/HPC expert by the European Commission, he has authored over 160 scientific papers. His research focuses on Computer Architecture, including Embedded Systems, Multiprocessors, Memory Performance, Workload Characterization, and Reconfigurable Computing. He is a Lifetime Member of ACM and a Senior Member of IEEE and the IEEE Computer Society.