2026-06-10 –, Poster Island D
Processor implementations designed to occupy minimal areas, such as SERV or FazyRV, are becoming increasingly popular. Some of these designs focus on flexibility and configurability while maintaining their compact design. However, due to their minimal area, implementations often involve compromises in specific components to achieve this level of efficiency. The FazyRV decoder, e.g., is highly optimized for area and therefore omits certain checks for illegal instructions.
To address these drawbacks, we propose a concept that uses partial runtime reconfiguration to dynamically replace the decoder's logic with a more robust variant to enable stricter instruction checking. These modifications introduce an area overhead of up to 39% more flip-flops than the original implementation. Dynamic partial reconfiguration can be triggered during runtime via a memory-mapped register, enabling the processor to continue normal operation seamlessly.
I'm an Assistant Professor of Reconfigurable Computer Architectures in the Embedded Architectures & Systems Group at the Institute of Technical Informatics, Graz University of Technology and a RISC-V Advocate. I completed my PhD under Prof. Marcel Baunach, earning the Doctor of Engineering Sciences (Dr. techn.) degree sub auspiciis Praesidentis. My research focuses on sustainable, flexible, and runtime-reconfigurable microcontroller architectures for embedded systems – especially FPGA-based RISC-V – at the hardware-software interface, including processor logic and embedded operating systems. I teach CPU architecture and implementation, embedded programming, and scientific writing. I have authored peer-reviewed publications in international journals and conference proceedings and am active in several RISC-V SIGs, Euromicro, the ACM, and the German Informatics Society (GI).
