Functional verification dominates modern SoC development effort, yet migrating simulation testbenches to FPGA emulation typically requires proprietary tools, expensive licenses, and
significant manual RTL adaptation-particularly for designs using DPI-C calls, multi-cycle timing blocks, or system tasks like $display and $finish. We present Loom, a fully open-source
toolchain that automatically transforms unmodified simulation-grade SystemVerilog into FPGA-synthesizable RTL with complete host communication infrastructure. Built on Yosys, Loom
applies five composable compiler passes-memory shadowing, reset extraction, DPI-C bridge instrumentation, scan chain insertion, and AXI-Lite emulation wrapping-to close the semantic
gap between simulation and emulation. We validate Loom end-to-end on a Snitch RISC-V core running on a Xilinx Alveo U250 with no manual source modifications, demonstrating DPI argument
passing, scan-based state capture/restore, and host memory preloading via PCIe XDMA.