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UID:pretalx-eu-summit-2026-97EAVY@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T110000
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DESCRIPTION:Custom RISC‑V implementations increasingly require tight coup
 ling between hardware and software development to ensure correctness\, per
 formance\, and rapid iteration. This paper presents the RISC‑V Unified D
 B Instruction Set Simulator (RVUDB‑ISS)\, an open-source simulation‑dr
 iven framework that enables early‑stage HW/SW co‑development\, configu
 ration validation\, and full‑stack debug prior to RTL availability. The 
 ISS is automatically generated from a formally specified configuration\, p
 roducing an implementation‑accurate model for custom RISC‑V cores and 
 extensions. \n\nRVUDB‑ISS supports configuration‑optimized binaries\, 
 enforcement of architectural corner cases\, and precise modeling of implem
 entation‑defined behaviors. \nA key functionality is the ISS’s integra
 ted debug experience: developers can run custom workloads\, halt execution
  at the first instruction\, and attach standard tools such as GDB and VS C
 ode to provide a familiar SW debug environment. This enables full symbolic
  debug of custom cores without hardware availability\, significantly reduc
 ing time‑to‑bring up\, and improving quality at bring up. \n\nOverall\
 , RVUDB‑ISS demonstrates that simulation‑based debug for custom RISC
 ‑V configurations enables earlier validation\, higher code quality\, and
  more reliable HW/SW co‑development compared to traditional pre and post
 ‑silicon workflows.
DTSTAMP:20260522T163158Z
LOCATION:Poster Island A
SUMMARY:Simulation-Driven Framework for Custom RISC-V HW/SW Co-Development 
 and Debug - Henrik Gustafsson
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/97EAVY/
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