Custom RISC‑V implementations increasingly require tight coupling between hardware and software development to ensure correctness, performance, and rapid iteration. This paper presents the RISC‑V Unified DB Instruction Set Simulator (RVUDB‑ISS), an open-source simulation‑driven framework that enables early‑stage HW/SW co‑development, configuration validation, and full‑stack debug prior to RTL availability. The ISS is automatically generated from a formally specified configuration, producing an implementation‑accurate model for custom RISC‑V cores and extensions.

RVUDB‑ISS supports configuration‑optimized binaries, enforcement of architectural corner cases, and precise modeling of implementation‑defined behaviors.
A key functionality is the ISS’s integrated debug experience: developers can run custom workloads, halt execution at the first instruction, and attach standard tools such as GDB and VS Code to provide a familiar SW debug environment. This enables full symbolic debug of custom cores without hardware availability, significantly reducing time‑to‑bring up, and improving quality at bring up.

Overall, RVUDB‑ISS demonstrates that simulation‑based debug for custom RISC‑V configurations enables earlier validation, higher code quality, and more reliable HW/SW co‑development compared to traditional pre and post‑silicon workflows.