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UID:pretalx-eu-summit-2026-9MT9QK@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T105000
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DESCRIPTION:The development of our tightly coupled SIMD/Vector accelerator 
 for matrix operations requires extending the RISC-V instruction set. Speci
 al compiler support is required for this extension. Our methodology starts
  from a Sail description of the ISA extension and generates the compiler t
 arget description data. The instructions are described in Sail and are tes
 ted in the generated simulator. The compiler is generated from the descrip
 tion model and is tested with the accelerator implemented in hardware. The
  experimental results suggest that for matrix multiplication we obtained s
 peed-ups up to 1413x compared to an ARM A72 core.
DTSTAMP:20260522T163242Z
LOCATION:Poster Island C
SUMMARY:Custom RISC‑V SIMD Matrix Extensions with LLVM Support - Alexandr
 u Puscasu\, Catalin Ciobanu
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/9MT9QK/
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