Memory zeroing is a common operation for enforcing system security. Zeroing is used to clear memory contents to prevent information leakage and initialise memory contents to prevent uninitialized memory access. Vendors such as Intel and ARM support fast memory zeroing instructions to improve system performance efficiency. The cache management operation (CMO) extension has also been recently been added to RISC-V which can be used for improving memory zeroing performance. Compared to the standard systems, memory zeroing is more frequently used in capability systems such as CHERI to prevent capability leakage. In this work, we evaluate different memory zeroing strategies on CHERI, and implement hardware support for improving the performance and efficiency of memory zeroing on CHERI-Toooba: a CHERI-extended RISC-V CPU.