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UID:pretalx-eu-summit-2026-A8BV3C@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T132000
DTEND;TZID=CET:20260611T133000
DESCRIPTION:Communication baseband workloads such as covariance estimation\
 , synchronization and reduction operations exhibit substantial data-level 
 parallelism. The RISC-V Vector Extension (RVV) introduces vector-length ag
 nostic (VLA) execution\, enabling scalable vector implementations independ
 ent of a fixed hardware width. In this work\, we explore architectural sca
 lability trade-offs of a configurable RVV-based vector processor across VL
 EN\, lane count\, and lane width. Using representative communication kerne
 ls and synthesis with the predictive ASAP7 PDK\, we analyze architectural 
 scaling behavior and the interaction between cycle reduction and frequency
  degradation. While increasing VLEN reduces cycle counts\, critical-path g
 rowth and bandwidth imbalance introduce a parallelism–frequency trade-of
 f that yields kernel-dependent optimal configurations. We further demonstr
 ate how a lightweight custom vector complex multiplication instruction imp
 roves efficiency for covariance-based workloads. The results highlight the
  importance of balanced compute–memory design for practical and physical
 ly realizable RVV implementations.
DTSTAMP:20260522T163204Z
LOCATION:Poster Island B
SUMMARY:Architectural Scalability Trade-Offs in an RISC-V Vector Processor 
 for Communication Kernels - Keivan Fayyazifard
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/A8BV3C/
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