2026-06-11 –, Poster Island B
The transputer is a famous High Performance Computing (HPC) architecture from the late 1980s/early 1990s, with Inmos being arguably the most famous example. Embodying a communication-centric, distributed-memory MIMD architecture designed explicitly for scalable parallel process networks, there are numerous potential efficiency advantages to this approach. In a world where scientific programmers are ever demanding more performance, but having to balance this with energy efficiency, this approach is worth another look. The Esperanto ET-SoC-1 was a 1,088-core RISC-V manycore accelerator organised around a mesh network-on-chip (NoC) with hierarchical cache and scratchpad memory structures. Purchased and released by the AI foundry who are focussed on open source, they are emphasising the transputer credentials of the architecture. In this abstract and associated poster we provide and independent exploration around how parallel code written for a T800 transputer array may be systematically mirrored onto the ET-SoC-1 compute fabric. We identify architectural similarities and highlight key divergences.
Having successfully completed an MSc in High Performance Computing at EPCC, I decided to continue on to PhD research focusing on the opportunities that RISC-V technology brings to HPC.
The central hypothesis of this research is that emerging RISC-V Integrated Matrix Extension (IME) can provide a scalable, efficient and performant foundation for HPC workloads. New compiler and programming-model abstractions developed to expose and optimise matrix-centric execution in a portable and reproducible manner would provide a platform to evaluate these benefits.