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UID:pretalx-eu-summit-2026-AHPSLC@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T134000
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DESCRIPTION:Vector architectures are widely used in multicore systems to ex
 ploit data-level parallelism\, but their bursty\, high-bandwidth memory be
 havior can exacerbate contention for shared resources such as caches and D
 RAM\, increasing timing variability. This paper introduces the principles 
 behind InterFinder\, a unified interference analysis framework for RISC-V 
 vector architectures that combines compiler-based analysis\, formal SW/HW 
 modeling\, and microarchitectural abstraction to support interference-awar
 e timing analysis.
DTSTAMP:20260609T203752Z
LOCATION:Poster Island C
SUMMARY:InterFinder: A Framework for Memory Interference Analysis in RISC-V
  Vectors - Oumaima Matoussi
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/AHPSLC/
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