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UID:pretalx-eu-summit-2026-ALLVDR@cfp.riscv-europe.org
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DESCRIPTION:In this paper we present STRiVe-VP\, a hybrid RISC-V simulation
  framework that unifies functional and timing simulation by leveraging LLV
 M’s compiler infrastructure. Built on RISC-V VP++\, it translates execut
 ed instructions into LLVM MCInst and LLVM MCA Instruction objects\, which 
 are injected into an extended LLVM MCA pipeline. Custom hardware units (ca
 che\, prefetch buffer\, branch predictor) are modeled\, allowing the combi
 nation of static scheduling information with dynamic effects from control 
 flow and memory behavior. This direct integration enables timing-aware dec
 isions using live architectural state and provides unified functional and 
 timing debugging. Validation against an FPGA prototype of an in-order\, si
 ngle-issue rv32emc_zfinx core shows that STRiVe-VP matches FPGA cycle coun
 ts exactly for several benchmarks and across multiple optimization levels\
 , demonstrating cycle-accurate performance estimation and a solid basis fo
 r extending to more complex RISC-V microarchitectures.
DTSTAMP:20260522T163129Z
LOCATION:Poster Island B
SUMMARY:STRiVe-VP: LLVM-based performance simulator for RISC-V processors -
  Giorgio Marletta\, Giovanni Di Guardo
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/ALLVDR/
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