In this paper we present STRiVe-VP, a hybrid RISC-V simulation framework that unifies functional and timing simulation by leveraging LLVM’s compiler infrastructure. Built on RISC-V VP++, it translates executed instructions into LLVM MCInst and LLVM MCA Instruction objects, which are injected into an extended LLVM MCA pipeline. Custom hardware units (cache, prefetch buffer, branch predictor) are modeled, allowing the combination of static scheduling information with dynamic effects from control flow and memory behavior. This direct integration enables timing-aware decisions using live architectural state and provides unified functional and timing debugging. Validation against an FPGA prototype of an in-order, single-issue rv32emc_zfinx core shows that STRiVe-VP matches FPGA cycle counts exactly for several benchmarks and across multiple optimization levels, demonstrating cycle-accurate performance estimation and a solid basis for extending to more complex RISC-V microarchitectures.