The semiconductor industry increasingly requires engineers skilled in both hardware design and software execution. This contribution presents a RISC-V-centric educational pipeline developed at our institute, bridging foundational bachelor's coursework and specialized master's programs. We outline three core courses that integrate practical hardware design, custom ISA extensions, and full-stack security. First, a computer organization course teaches students hardware design in SystemVerilog with the goal of modifying and extending a full RISC-V CPU. Second, a hardware security course tasks students with both the implementation of security-related hardware primitives for open-source RISC-V cores, and the development of software to interact with the extended hardware. Finally, a secure system architectures course addresses memory safety through full system prototyping, requiring students to modify the RISC-V Spike simulator and write custom LLVM compiler passes. This hands-on approach provides the ecosystem with engineers equipped to tackle modern microarchitectural and security challenges.