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UID:pretalx-eu-summit-2026-B8BJHQ@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T154000
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DESCRIPTION:Functional verification of RISC-V multi-core IPs is bottleneck 
 by the sequential nature of convectional CPU-based event driven simulation
 \, where coverage closure timelines scale linearly with core count and con
 figuration complexity. This paper presents a GPU- accelerated parallel sim
 ulation framework that offloads stimulus generation\, constraint solving\,
  and concurrent coverage computation to GPU hardware while retaining UVM t
 estbench orchestration on the CPU host. The framework employs a heterogene
 ous partitioning tasks including constrained-random transaction generation
 \, functional coverage bin evaluation\, and reference model computation ar
 e parallelized across GPU threads using CUDA kernels. The control\, DUT RT
 L simulation\, and sequential verification logic\, ensuring complete compa
 tibility with existing verification flows. Evaluated on RISC-V IP configur
 ations ranging from 2 to 32 cores with AXI4 interconnect and MESI coherenc
 y protocol\, the framework achieves up to 22x simulation speedup\, reduces
  coverage closure time from 44 hours to 14 hours\, and reaches 99 percent 
 functional coverage versus 93 percent for CPU-only baselines within the sa
 me wall clock budget. The GPU acceleration advantage scales near -linearly
  with core count\, making it particularly valuable for emerging many core 
 RISC-V designs targeting automotive and data-center applications. The appr
 oach requires no modification to existing RTL or UVM testbench architectur
 es\, integrating via a lightweight GPU dispatch layer that operates on sta
 ndard simulation interfaces.
DTSTAMP:20260522T163251Z
LOCATION:Poster Island B
SUMMARY:GPU-Accelerated Parallel Simulation for RISC-V Multi-Core IP Verifi
 cation - Abinaya Senthil
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/B8BJHQ/
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