2026-06-10 –, Poster Island B
Functional verification of RISC-V multi-core IPs is bottleneck by the sequential nature of convectional CPU-based event driven simulation, where coverage closure timelines scale linearly with core count and configuration complexity. This paper presents a GPU- accelerated parallel simulation framework that offloads stimulus generation, constraint solving, and concurrent coverage computation to GPU hardware while retaining UVM testbench orchestration on the CPU host. The framework employs a heterogeneous partitioning tasks including constrained-random transaction generation, functional coverage bin evaluation, and reference model computation are parallelized across GPU threads using CUDA kernels. The control, DUT RTL simulation, and sequential verification logic, ensuring complete compatibility with existing verification flows. Evaluated on RISC-V IP configurations ranging from 2 to 32 cores with AXI4 interconnect and MESI coherency protocol, the framework achieves up to 22x simulation speedup, reduces coverage closure time from 44 hours to 14 hours, and reaches 99 percent functional coverage versus 93 percent for CPU-only baselines within the same wall clock budget. The GPU acceleration advantage scales near -linearly with core count, making it particularly valuable for emerging many core RISC-V designs targeting automotive and data-center applications. The approach requires no modification to existing RTL or UVM testbench architectures, integrating via a lightweight GPU dispatch layer that operates on standard simulation interfaces.
This work addresses the growing simulation bottleneck in RISC-V multi-core verification by leveraging GPU parallelism for stimulus generation and coverage computation. It is relevant to the RISC-V community because verification cost dominates development timelines, especially as core counts increase. The framework fosters ecosystem growth by enabling smaller verification teams to achieve coverage closure on complex multi-core designs using commodity GPU hardware rather than expensive emulation platforms. Target audience include verification engineers, IP designers, and EDA researchers working on RISC-V multi core SoCs.
Abinaya Senthil is a Design Verification Engineer at NXP Semiconductors, Austin, Texas specializing in UVM-based IP verification, System Verilog, CDC verification, and memory injection methodologies for complex IP designs. She is a founder of SiliconDV , a technical education platform for semiconductor verification engineers. She is a member on the IEEE WIE MRP award review committee and has presented CSTIC 2026 ( IEEE Xplore indexed). Her research focus on AI-driven verification optimization and GPU accelerated simulation for RISC-V architectures.