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UID:pretalx-eu-summit-2026-BLF3DX@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T143000
DTEND;TZID=CET:20260610T144500
DESCRIPTION:When the RISC-V matrix extensions effort was restructured into 
 four complementary approaches at Summit Europe 2025 in Paris\, it was a bo
 ld architectural bet — that the breadth of the RISC-V ecosystem demands 
 not one rigid solution but a family of extensions spanning from lightweigh
 t vector-matrix primitives to fully independent matrix engines. One year l
 ater\, that bet is paying off. This talk reports on the rapid progress acr
 oss the matrix extension family as two of the four extensions — the Inte
 grated Matrix Extensions (IME) and the Vector Matrix Extensions (VME) — 
 converge on specification freeze. We trace the architectural decisions tha
 t brought IME and VME from concept to maturity: algebraic tile geometry th
 at scales naturally with VLEN\, the deliberate reuse of RVV state for seam
 less software integration\, and the introduction of dedicated accumulator 
 registers to unlock higher computational intensity where implementations d
 emand it. Crucially\, work is starting to unify IME and VME through a comm
 on LLVM-MLIR lowering path — giving compilers and AI/ML frameworks a sin
 gle abstraction that targets both extensions\, ensuring that the software 
 ecosystem scales with the hardware rather than fragmenting across it. For 
 Europe's semiconductor industry — from research institutions and startup
 s to established design houses — standardized\, open matrix extensions r
 epresent a strategic opportunity: competitive AI/ML and HPC capability on 
 an open ISA\, free from proprietary lock-in. RISC-V matrix support is no l
 onger a roadmap item. It is arriving.
DTSTAMP:20260715T065423Z
LOCATION:Plenary
SUMMARY:Matrix Extensions for RISC-V: Delivering on the Promise - Dr. Phili
 pp Tomsich
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/BLF3DX/
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