The RISC-V architecture has experienced rapid growth in recent years, evolving from an academic research project into a global ecosystem spanning industry, academia, and open-source communities. However, achieving competitive application performance across the diverse RISC-V microarchitectures requires a mature compiler infrastructure capable of realizing the performance potential of the underlying hardware. In this work, we present XSCC, a high-performance compiler built on LLVM 19.1.0, designed to meet industrial-grade performance demands while actively contributing to open-source ecosystem development. XSCC performs a systematic cross-architecture optimization analysis, distilling compiler insights from mature architectures into a cohesive set of optimizations for RISC-V, including enhanced loop transformations, memory access reordering, and microarchitecture-specific scheduling models. Four of these optimizations have been upstreamed to the LLVM project. Experimental evaluation demonstrates consistent improvements over baseline LLVM 19 and GCC 12, achieving up to 1.14x speedup on SPEC CPU 2006 FP on the simulated XiangShan KMHv3 and up to 1.30x speedup on SPEC CPU 2006 INT on commercial RISC-V hardware SpacemiT X60.