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UID:pretalx-eu-summit-2026-CBLJYX@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T161000
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DESCRIPTION:Verifying modern RISC-V cores requires qualifying every merge r
 equest (MR) against a large and evolving test space spanning ISA extension
 s\, micro-architectural features\, and system-level scenarios. Manually se
 lecting appropriate tests for each MR is time-consuming and error-prone\, 
 and does not scale with the rate of RTL changes. This work presents an AI-
 driven testlist generator that automatically derives MR-specific regressio
 n lists for a production RISC-V core verification environment. The tool an
 alyzes Git diffs for an MR\, infers impacted features using a combination 
 of static rules and large language models (LLMs)\, and synthesizes targete
 d regressions across multiple test generators. The resulting flow reduces 
 MR-qualification effort\, improves repeatability\, and provides a concrete
  path toward coverage-driven\, closed-loop test selection for RISC-V core 
 verification.
DTSTAMP:20260522T163244Z
LOCATION:Poster Island A
SUMMARY:AI-Driven Testlist Generation for RISC-V Core Verification - Vikas 
 Dubey\, Abhishek Rajgadia\, Shubham Singla\, Radha Govindaradjou
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/CBLJYX/
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