2026-06-09 –, Poster Island C
The RISC-V instruction set architecture (ISA) has seen rapid adoption over the past few years. Despite
this growth, the software ecosystem remains a major challenge to broader adoption. In contrast to x86 and ARM platforms, where precompiled binaries are widely available, RISC-V developers often face a significant software availability gap. Consequently, many packages, libraries, or applications must be built from source, requiring substantial expertise in build systems and target architectures. This process is largely manual and time-consuming, creating a significant barrier to widespread adoption of the RISC-V. To address this critical gap, this paper presents ATESOR, a multi-stage LLM-based framework for autonomous RISC-V software porting. The framework uses large language models to plan build requirements, compile packages, debug failures, and test generated binaries in RISC-V sandboxed environments. ATESOR supports both containerized RISC-V environment and native execution on RISC-V hardware such as the Banana Pi BPI-F3 and Milk-V Pioneer, provided by Cloud-V. ATESOR is trained on an internal dataset of more than 500 manually ported packages spanning build systems including CMake, Make, Ninja, and Go. For 100 CMake and Go-based packages, ATESOR demonstrated a 80% successful porting rate and experiment completed in approximately 1.5 hours, corresponding to an average porting time of about 54 seconds per package.
Software porting often requires deep expertise in target architectures, build systems, and toolchain integration, skills that are not widely available and impose significant manual effort
and time costs. To address these challenges, this paper introduces ATESOR, multi-stage, LLM-based framework for autonomous RISC-V software porting. ATESOR uses LLMs with tool-use capabilities to execute a four-stage pipeline: (1) analysis and planning of architecture specific requirements, (2) autonomous generation of build plans and corresponding patches, (3) execution
of the build in a RISC-V sandbox environment with automated issue resolution, and (4) verification of build steps and resulting binaries to ensure correctness and reproducibility.
To the best of our knowledge, ATESOR is the first LLM-based framework specifically designed for RISCV software porting. The system is trained on an internal dataset comprising over 500 manually ported
packages, libraries, and applications, covering a variety of build systems including CMake, Make, and
Go, enabling robust learning of architecture-specific
build patterns and porting strategies.
Akif has done in BS in Computer Engineering from ITU Lahore, Pakistan. He has 3+ years of experience in the semiconductor industry, specializing in RISC-V software. His work spans multiple OSes, RTOSes, and microkernel RISC-V enablement. Currently working as Systems/Firmware Engineer at 10xEngineers. He recently joined the Eclipse Foundation as a ThreadX RTOS committer. He is also a core member and developer of Cloud-V platform.