The increasing demand for domain-specific architectures from various domains such as Artificial Intelligence (AI),High Performance Computing (HPC), and automotive systems is reshaping modern System on Chip (SoC) design,requiring faster iteration cycles and deeper hardware/software integration. While the open ISA RISC-V enablesunprecedented architectural flexibility, it also dramatically expands the design space across system, micro-architectural,and implementation levels. Efficiently navigating this complexity remains a key challenge for both academia and industry.The A-DECA framework is a design space exploration framework developed within the SoC Planner project to accelerateproductive SoC design. A-DECA enables a structured and modular exploration from high-level architectural configurationdown to synthesis-aware micro-architectural evaluation, effectively bridging the gap between system-level modeling andimplementation constraints.Our methodology leverage the open-source RISC-V design flow Chipyard to develop a hardware/software co-designsolution that supports automated configuration generation, parameter tuning, and quantitative performance, power, areatrade-off analysis. By reducing manual exploration effort and formalizing early-stage architectural planning, A-DECAsignificantly improves design productivity and accelerates pre-silicon decision-making. The framework reinforces theopen-source chip design ecosystem and lays the foundation for scalable, chiplet-oriented RISC-V architectures. Its plannedopen-source release aims to further enable reproducible research, industrial adoption, and collaborative innovation infull-flow RISC-V SoC development.