BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//pretalx//cfp.riscv-europe.org//eu-summit-2026//talk//DZKKKP
BEGIN:VTIMEZONE
TZID:CET
BEGIN:STANDARD
DTSTART:20001029T040000
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10
TZNAME:CET
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
END:STANDARD
BEGIN:DAYLIGHT
DTSTART:20000326T030000
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3
TZNAME:CEST
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
END:DAYLIGHT
END:VTIMEZONE
BEGIN:VEVENT
UID:pretalx-eu-summit-2026-DZKKKP@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T111000
DTEND;TZID=CET:20260609T112000
DESCRIPTION:Mitigating transient execution attacks like Spectre in RISC-V p
 rocessors requires cycle-accurate Register Transfer Level (RTL) simulation
 . However\, existing methodologies face a severe dichotomy: simple bare-me
 tal benchmarks lack crucial architectural features (e.g.\, virtual memory\
 , privilege boundaries)\, while full-OS simulations incur prohibitive exec
 ution times. To bridge this gap\, we propose a novel\, lightweight RTL sim
 ulation framework that accurately models cross-privilege transitions (User
  and Supervisor modes) and virtual address translation without the overhea
 d of a full OS payload. We validated this approach by simulating a realist
 ic\, cross-privilege Spectre-PHT attack on the out-of-order NaxRiscv core\
 , achieving secret recovery in approximately 100\,000 cycles. This drastic
 ally accelerates vulnerability characterization compared to Linux-boot env
 ironments. Ultimately\, this low-noise environment provides hardware desig
 ners with an efficient tool to rapidly analyze transient vulnerabilities a
 nd evaluate the performance overhead of hardware countermeasures.
DTSTAMP:20260522T163244Z
LOCATION:Poster Island A
SUMMARY:Beyond Bare-Metal: A Lightweight Cross-Privilege Framework for RISC
 -V RTL Security Evaluation - Karim AIT LAHSSAINE
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/DZKKKP/
END:VEVENT
END:VCALENDAR