We present HBENCH, a microbenchmark suite for instruction-level characterization of RISC-V (scalar and RISC-V Vector Extension (RVV)) and x86 (scalar and Advanced Vector Extensions (AVX)2), enabling accurate simulator performance models. HBENCH maps scalar and vector microkernels to gem5 latency groups and reports latency and peak throughput for Floating-Point (FP)32, FP64, and Integer (INT) operations. We evaluate a Banana Pi F3 (SpacemiT K1, X60, RVV 1.0, 256-bit Vector Length (VLEN)) and derive a gem5-compatible performance model. Coverage is validated against RIVEC workloads using dominant RVV instruction mixes.
Our results span over 329 microkernels, providing per-latency-group latency and throughput, cache hierarchy probes, and Instructions Per Cycle (IPC)-based classification, demonstrating HBENCH’s ability to support high-accuracy instruction-level performance modeling.