2026-06-11 –, Poster Island A
AI and HPC workloads demand scalable, efficient accelerator architectures. We present MAGIA-V, an open mesh-of-tiles accelerator template integrating a RISC-V Zve32d Spatz vector processor with a RedMulE tensor engine, enabling concurrent vector and matrix operations.
Electronic Engineer with a BSc (2023) and MSc (2026) in Electronic Engineering from the University of Bologna. Currently a Researcher at Fondazione Chips-IT, focused on the design and development of RISC-V-based processors, accelerators, and SoCs.
Alessandro Nadalini received the B.Sc. and M.Sc. degrees in electronic engineering from the University of Bologna in 2018 and 2021, respectively. He is currently pursuing the Ph.D. degree with the Department of Electrical, Electronic and Information Technologies Engineering (DEI), University of Bologna. His research regards the hardware-software co-design of multi-processors heterogeneous systems on chip. He received the Mukherjee Best Paper Award of the 2023 IEEE Computer Society Annual Symposium on VLSI.