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UID:pretalx-eu-summit-2026-ETWYRB@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T140000
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DESCRIPTION:In this work\, we present a dedicated IP core optimized for ene
 rgy-efficient convolution over highly sparse and unstructured input arrays
 \, characteristic of event-based convolutional neural networks. The accele
 rator was integrated into a RISC-V-enabled system on chip (SoC) and taped 
 out in 65nm TSMC technology to enable full post silicon characterization a
 nd to evaluate alternative sparse computation algorithm variants.
DTSTAMP:20260715T065840Z
LOCATION:Poster Island A
SUMMARY:RISC-V Based SoC for Event-Based Sparse Convolutions - Diego Gigena
  Ivanovich
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/ETWYRB/
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