2026-06-11 –, Poster Island A
In this work, we present a dedicated IP core optimized for energy-efficient convolution over highly sparse and unstructured input arrays, characteristic of event-based convolutional neural networks. The accelerator was integrated into a RISC-V-enabled system on chip (SoC) and taped out in 65nm TSMC technology to enable full post silicon characterization and to evaluate alternative sparse computation algorithm variants.
Diego Gigena Ivanovich is a Scientist at Silicon Austria Labs (SAL), where he conducts research on microelectronics for embedded artificial intelligence. His work focuses on the design and optimization of hardware accelerators for AI applications in embedded systems. He holds a Ph.D. in Electrical Engineering from the National University of the South (Argentina).