2026-06-11 –, Plenary
The emergence of RISC-V as an open and extensible instruction set architecture has enabled the development of domain-specific accelerators and General-Purpose Graphics Processing Units (GPGPUs). While the RISC-V ISA provides support for scalar instructions and the RISC-V Vector Extension (RVV) enables data-parallel vector execution, these models do not directly support the Single-Instruction Multiple-Thread (SIMT) execution paradigm required by modern GPU architectures. Consequently, efficient software enablement for RISC-V–based GPUs requires compiler support capable of generating SIMT-oriented instruction sequences and managing massively parallel execution. This proposal talks about CHAKRA-GP, a hardware-optimized compiler framework for RISC-V–based GPGPU architectures. Built upon LLVM and MLIR infrastructures, CHAKRA-GP provides a scalable compilation pipeline enabling efficient kernel generation, memory optimization, and parallel execution mapping for massively parallel workloads. The compiler targets custom RISC-V GPGPU platforms and enables efficient execution of HPC, scientific computing, and AI workloads. The work demonstrates how an extensible compiler infrastructure can bridge the gap between the RISC-V ISA and SIMT-based GPU execution models, enabling efficient compilation for customizable RISC-V GPGPU architectures.
This work presents CHAKRA-GP, a compiler framework targeting RISC-V–based GPGPUs that combines domain-specific optimization pipelines with unified LLVM-based code generation. HPC workloads are compiled through a direct LLVM [5] optimization flow that generates SIMT [6][7] execution and custom memory instructions optimized for throughput-oriented computation. AI workloads are processed using an MLIR-based [8] pipeline that preserves tensor semantics and performs structured transformations before lowering to LLVM IR for final instruction generation targeting tensor and matrix compute cores.
By integrating MLIR-driven high-level optimization with LLVM’s mature backend infrastructure, CHAKRA-GP enables efficient mapping of heterogeneous workloads onto customizable RISC-V GPU architectures while maintaining retargetability across evolving designs. The proposed approach demonstrates how compiler architecture can support co-design of open GPU hardware and software ecosystems for next-generation HPC and AI platforms.
Ms. Prachi Pandey is a Senior Compiler Engineer at C-DAC, where she works on MLIR/LLVM-based compiler development for indigenous processors, GPUs, and AI accelerators. She has nearly two decades of experience in HPC, parallel programming, compilers, and runtime systems. Her research interests include compiler optimization techniques, automatic parallelizing compilers, performance portability for heterogeneous architectures, and parallelization strategies for HPC and AI workloads.
