2026-06-11 –, Poster Island A
The Fast Fourier Transform (FFT) is a key operation in digital signal processing. Real-time applications on edge devices require fast FFT computations under strict power and hardware constraints. Standalone FFT accelerators meet the performance need but add chip area and power, which makes them a poor fit for resource-limited systems.
This paper presents APEX, a tightly-coupled coprocessor integrated with the CV32A6 RISC-V CPU pipeline via the CORE-V eXtension interface (CV-X-IF). The core butterfly operations are offloaded to a coprocessor through custom instructions. For fixed-point FFT data of size N=512, APEX reduces execution cycles by 83.5% and instruction count by 87.9% compared to the software FFT on the baseline CPU. On FPGA, it preserves the baseline operating frequency with only minimal area overhead. These results demonstrate that APEX is an efficient and practical solution for accelerating FFT-intensive workloads in embedded and edge systems built on open RISC-V architectures.
I am an ASIC Design Engineer working on a CPU Subsystem from the ISA and Microarchitecture Specification to RTL implementation, functional verification, synthesis, and timing closure. I am experienced in Hardware-software co-design, developing custom ISA instruction specifications and implementing tightly coupled and coarse-grained co-processors for FFT and Neural Network workloads. I have also been involved in working across the HW/SW stack, from application, compiler, architecture, and implementation. I have been an active contributor to open-source CPU designs (CVA6, SERV) and RISC-V architecture compatibility test suite (ACTs) development.