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UID:pretalx-eu-summit-2026-FWXFHU@cfp.riscv-europe.org
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DESCRIPTION:Modern processors implement complex features that require uniqu
 e verification strategies to exhaustively verify the feature and achieve c
 overage goals faster. The memory management unit (MMU) within the CVA6\, w
 ith multiple level of table\, page tables\, lookaside buffers (TLBs)\, and
  physical memory protection (PMP) capabilities\, is one such feature. It i
 s highly configurable and complex\, making an exhaustive verification a re
 al challenge. It requires smart management of different page table entries
  (PTEs) and PMP entries\, to simulate different types of exceptions\, page
  faults and PMP access errors. This work is done using an Universal Verifi
 cation Method (UVM) framework provinding an efficient means creating PMPs 
 and PTEs\, thus simplifying the verification of MMU.
DTSTAMP:20260522T163254Z
LOCATION:Poster Island A
SUMMARY:Functional Verification Strategy for a CVA6 MMU - Tanuj Khandelwal
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/FWXFHU/
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