Modern processors implement complex features that require unique verification strategies to exhaustively verify the feature and achieve coverage goals faster. The memory management unit (MMU) within the CVA6, with multiple level of table, page tables, lookaside buffers (TLBs), and physical memory protection (PMP) capabilities, is one such feature. It is highly configurable and complex, making an exhaustive verification a real challenge. It requires smart management of different page table entries (PTEs) and PMP entries, to simulate different types of exceptions, page faults and PMP access errors. This work is done using an Universal Verification Method (UVM) framework provinding an efficient means creating PMPs and PTEs, thus simplifying the verification of MMU.