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UID:pretalx-eu-summit-2026-G7Y79Q@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T121500
DTEND;TZID=CET:20260611T123000
DESCRIPTION:Modern data-centric workloads increasingly expose the limitatio
 ns of traditional von Neumann architectures\, where excessive data movemen
 t limits throughput and energy efficiency.\n        While hardware acceler
 ators improve performance\, they often lack flexibility and still require 
 costly memory transfers.\n        Existing compute in- and near-memory sol
 utions reduce the memory bottleneck but introduce usability challenges rel
 ated to constraints on data placement.\n        ARCANE is a cache architec
 ture that doubles as a tightly-coupled near-memory coprocessor.\n        T
 he embedded RISC-V cache controller executes custom instructions offloaded
  by the host CPU relying on near-memory vector processing units within the
  cache memory subsystem. This architecture hides memory synchronization an
 d data mapping from application software\, while offering software-based I
 nstruction Set Architecture extensibility.\n        Evaluations demonstrat
 e up to an 84x speedup on 8-bit convolution layers over a traditional syst
 em-on-chip\, incurring only a 41.3\\% area overhead.
DTSTAMP:20260522T163242Z
LOCATION:Plenary
SUMMARY:ARCANE: Enabling High-Performance In-Cache Tensor Extensions in RIS
 C-V - Flavia Guella\, Vincenzo Petrolo
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/G7Y79Q/
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