2026-06-10 –, Plenary
Energy saving is a top priority for STMicroelectronics products. For the STxP5 embedded CPU based on the RISC-V architecture, there is a particular focus on minimizing static power when the core is inactive. Additionally, it is important to optimize the CPU restart time, silicon area, implementation complexity, and software overhead. The Ultra Low Power Retention with Warm Restart Mode addresses these challenges by maximizing power savings and reducing drawbacks typically associated with resuming operation. This solution leverages the modular, scalable, customizable, and extensible nature of the RISC-V architecture by defining and implementing a custom RISC-V extension and tailored microarchitecture.
This paper details the concrete microarchitectural and system mechanisms used to realize the Ultra Low Power Retention with Warm Restart Mode on an in‑house RV32, 4‑stage RISC‑V core family. Beyond the abstract, it precisely defines the power partitioning strategy, where the core power domain is fully shut down while TCMs remain in retention, and explains the implications on context handling, including architectural, non‑architectural, and hardware‑updated read‑only registers.
A central contribution is the XSTULP custom extension, mapped in the custom‑0 opcode space, which introduces two atomic instructions, XSTULP.gtr and XSTULP.rtr. These instructions micro‑sequence optimized internal operations (register access, memory transfers with pre/post‑update of a hidden stack pointer XS) to perform complete context save/restore in hardware, while software only needs to prepare a retention stack in TCM and disable interrupts.
The paper also describes the request–acknowledge protocol between the core and SoC, specific usage of RISC-V CSR, and the dedicated warm_restart_sequence that determines whether execution follows the normal boot flow or a warm restart path. Finally, the authors report quantitative KPIs (power, latency, area, software overhead) and outline the verification methodology, including UPF‑based dynamic tests and formal verification, demonstrating robustness of the proposed low‑power mode.
Anne Merlande is a processor architect at STMicroelectronics in Grenoble, within the Computing and Compilers Center. As Senior Member of Technical Staff, her expertise field covers processor and system architecture, CPU microarchitecture and frontend design, low power and energy efficient subsystems, security and functional safety.
She graduated from Institut Supérieur d’Électronique de Paris in 1995 and joined STMicroelectronics in 1999, after four years as an ASIP designer at Matra. At STMicroelectronics, she has led the design of the ST200 processor families, acted as technical lead for ARM Cortex A subsystem frontend design, and led top level integration for automotive SoCs.
She currently works as Processor Architect on the STxP5 core family, with a particular focus on ultra low power operation, security, and functional safety.