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UID:pretalx-eu-summit-2026-G93SVJ@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T103000
DTEND;TZID=CET:20260611T104000
DESCRIPTION:Cryptographic hash algorithms for zero-knowledge proof systems 
 often rely on prime-field S-box kernels such as x⁷ mod p over 31-bit fie
 lds. We accelerate this class of S-box primitives on a 4×4 coarse-grained
  reconfigurable array (CGRA) integrated within a RISC-V SoC. As a case stu
 dy\, we use the BabyBear instantiation adopted by the state-of-the-art Pos
 eidon2 hash function\, employing Barrett reduction to avoid software divis
 ion on the host core. Our mapping decomposes operands into 8-bit limbs acr
 oss CGRA processing elements and exploits the toroidal mesh for carry prop
 agation in 4 hops. Compared to a hand-optimized baseline\, we achieve 1.26
 × speedup and 25.7% energy reduction\; versus an automatic compiler\, we 
 improve by 6.6× speedup and save 82% energy. Cycle-accurate RTL simulatio
 n of a full Poseidon2 integration shows ~3.3× fewer cycles than the RISC-
 V host for the full 141-invocation workload at 100 MHz (even a ~1.3× redu
 ction at 250 MHz).
DTSTAMP:20260522T163254Z
LOCATION:Poster Island A
SUMMARY:Accelerating the Poseidon2 S-box in a RISC-V SoC with a 4×4 CGRA -
  Cristian Campos
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/G93SVJ/
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