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UID:pretalx-eu-summit-2026-GE87GD@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T133000
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DESCRIPTION:Early-stage performance estimation plays a critical role in HW/
 SW co-design. It enables SW development prior to silicon availability whil
 e guiding HW architectural exploration. These activities are inherently it
 erative and therefore require simulation environments that are sufficientl
 y fast to evaluate SW optimizations and HW design alternatives efficiently
 .\nCycle-accurate simulators provide highly precise execution-time estimat
 ion but are often too slow for evaluating realistic workloads. Instruction
  Set Simulators (ISSs)\, in contrast\, offer significantly higher simulati
 on speed but lack accurate timing information. Abstract performance models
  represent a promising compromise\; however\, existing handcrafted approac
 hes remain labor-intensive and difficult to generalize.\nWe present an aut
 omated methodology for generating Machine Learning (ML)-based performance 
 models from cycle-accurate simulations and integrating them into fast ISS 
 environments. The approach targets the 64-bit RISC-V core CVA6 and is impl
 emented with the open-source emulator QEMU.
DTSTAMP:20260715T065812Z
LOCATION:Poster Island B
SUMMARY:Machine Learning-Based Performance Estimation for RISC-V Virtual Pr
 ototypes - Caaliph Andriamisaina
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/GE87GD/
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