Early-stage performance estimation plays a critical role in HW/SW co-design. It enables SW development prior to silicon availability while guiding HW architectural exploration. These activities are inherently iterative and therefore require simulation environments that are sufficiently fast to evaluate SW optimizations and HW design alternatives efficiently.
Cycle-accurate simulators provide highly precise execution-time estimation but are often too slow for evaluating realistic workloads. Instruction Set Simulators (ISSs), in contrast, offer significantly higher simulation speed but lack accurate timing information. Abstract performance models represent a promising compromise; however, existing handcrafted approaches remain labor-intensive and difficult to generalize.
We present an automated methodology for generating Machine Learning (ML)-based performance models from cycle-accurate simulations and integrating them into fast ISS environments. The approach targets the 64-bit RISC-V core CVA6 and is implemented with the open-source emulator QEMU.