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UID:pretalx-eu-summit-2026-H8SWVM@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T111000
DTEND;TZID=CET:20260611T112000
DESCRIPTION:The RISC-V ecosystem is moving toward increasingly heterogeneou
 s SoCs that combine multicore processors\, hardware accelerators\, and sof
 tware programmability. In this work\, we integrate the application-class C
 ORE-V CVA6 processor into the open-source ESP framework\, enabling ISA ext
 ensions within a coherent multicore platform. \nThe integration preserves 
 cache coherence\, SMP correctness\, and Linux-class software support\, whi
 le providing a practical path to deploying custom instructions in ESP-base
 d systems. To demonstrate the benefits of heterogeneity at the core level\
 , we implement an FFT butterfly extension using a CV-X-IF-based flow with 
 three custom instructions. Across FFT sizes from 16 to 1024 points\, the p
 roposed design achieves speedups of 1.37× to 1.45×.\nThese improvements 
 are obtained with low hardware overhead\, namely +0.23% at the platform le
 vel and +5% at the core level. Results show that ISA-level extensions can 
 complement multi-accelerator architectures by providing efficient fine-gra
 ined acceleration for recurring DSP kernels.
DTSTAMP:20260522T163447Z
LOCATION:Poster Island A
SUMMARY:Integration of CVA6 in ESP for ISA extensions and coherent multicor
 e: with FFT-butterfly instruction - rodrigo olmos
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/H8SWVM/
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