2026-06-11 –, Poster Island A
The RISC-V ecosystem is moving toward increasingly heterogeneous SoCs that combine multicore processors, hardware accelerators, and software programmability. In this work, we integrate the application-class CORE-V CVA6 processor into the open-source ESP framework, enabling ISA extensions within a coherent multicore platform.
The integration preserves cache coherence, SMP correctness, and Linux-class software support, while providing a practical path to deploying custom instructions in ESP-based systems. To demonstrate the benefits of heterogeneity at the core level, we implement an FFT butterfly extension using a CV-X-IF-based flow with three custom instructions. Across FFT sizes from 16 to 1024 points, the proposed design achieves speedups of 1.37× to 1.45×.
These improvements are obtained with low hardware overhead, namely +0.23% at the platform level and +5% at the core level. Results show that ISA-level extensions can complement multi-accelerator architectures by providing efficient fine-grained acceleration for recurring DSP kernels.
Integration of the CVA6 application-class RISC-V core into the ESP heterogeneous SoC framework, enabling coherent multicore execution and CV-X-IF-based ISA extensions. A custom FFT butterfly instruction is used as case study, showing low overhead and consistent speedup across FFT sizes.
Rodrigo Olmos is a researcher in heterogeneous RISC-V SoC design and hardware acceleration at Universidad Politécnica de Madrid (UPM). His work focuses on hardware/software co-design, multicore integration, custom ISA extensions, and FPGA-based prototyping for embedded and high-performance systems.