2026-06-10 –, Poster Island D
Modern processors delegate power and thermal management to dedicated Power Control Systems (PCS), communicating through kernel-mediated interfaces such as SCMI or the emerging RPMI.
Prior work has shown that end-to-end control quality is dominated by the power-management policy rather than by interface latency, leaving room to choose communication paradigms based on flexibility rather than raw latency.
We integrate Micro XRCE-DDS on ControlPULP, a RISC-V–based PCS, connecting it to a user-space Agent on an ARM host via a custom shared-memory transport.
This design removes protocol logic from kernel drivers and naturally supports multi-controller coordination through a shared middleware layer. Experiments on a ZCU102 FPGA at 20 MHz show 490 μs of active processing per publication, 0.8 MB/s throughput, and a memory footprint under 11.2 KB for 32 topics. The resulting latency is comparable to SCMI [1] while enabling a more flexible communication model.
I am a PhD student at the ECS Lab at University of Bologna, where I also earned my MSc in Electronics Engineering. My research focuses on digital architectures, with particular interest in RISC-V vector and matrix extensions and processing-in-memory (PIM) systems. I work on the Monte Cimone project, contributing to the enablement and characterization of the second-generation RISC-V cluster while evaluating the third iteration. I also contributed to AME-PIM, a novel approach that exposes PIM capabilities through the semantics of a matrix extension. In parallel, I work within the DARE project, where I contribute to the delivery of ControlPULP as the power-management controller for the GPP subsystem.
Antonio del Vecchio received his PhD in Electronic Engineering from the University of Bologna, where he also obtained his BSc and MSc degrees. His research focuses on power and thermal management for modern computing systems, with particular emphasis on high-performance computing, edge platforms, and RISC-V-based control architectures. During his PhD, he worked on open and scalable power-management subsystems, hardware/software communication interfaces, and thermal-power modeling techniques for many-core and chiplet-based processors. His work combines embedded systems, FPGA-based prototyping, firmware development, and system-level evaluation. His current interests include open RISC-V power controllers and flexible communication substrates for distributed, energy-efficient runtime management.