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UID:pretalx-eu-summit-2026-HMZYAS@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T154000
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DESCRIPTION:The growing demand for artificial intelligence\, scientific com
 puting\, and large-scale data analytics has significantly increased the ne
 ed for massively parallel computing architectures. Modern GPUs provide hig
 h computational throughput by executing thousands of concurrent threads\, 
 but most existing GPU architectures remain proprietary\, limiting open arc
 hitectural innovation and research. This paper presents Vishwa\, a scalabl
 e RISC-V based General Purpose GPU (GPGPU) architecture designed to enable
  open and extensible parallel computing platforms. The architecture adopts
  a hierarchical compute model composed of Vishwa Compute Clusters (VCLs) c
 ontaining multiple Vishwa Compute Cores (VCCs) that execute threads using 
 a Single Instruction Multiple Thread (SIMT) execution model. Each compute 
 core integrates specialised Vishwa Matrix Cores (VMCs) designed to acceler
 ate matrix-intensive operations commonly used in machine learning workload
 s. Work distribution across the architecture is managed by a global Vishwa
  Work Distributor (VWD) that schedules workloads across available compute 
 clusters. The architecture is supported by a complete software ecosystem t
 hrough the CHAKRA compiler stack\, which integrates with LLVM to provide k
 ernel compilation and runtime execution support. The compute core architec
 ture has been implemented and validated on an FPGA platform\, demonstratin
 g functional correctness of the execution pipeline and SIMT execution mode
 l.
DTSTAMP:20260522T163123Z
LOCATION:Poster Island C
SUMMARY:Vishwa: A Scalable RISC-V Based GPGPU - PRANOSE J EDAVOOR\, Prachi 
 Pandey\, Vivian
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/HMZYAS/
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