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UID:pretalx-eu-summit-2026-HZQQP9@cfp.riscv-europe.org
DTSTART;TZID=CET:20260609T110000
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DESCRIPTION:While hardware prefetchers accelerate memory performance\, they
  inadvertently leave microarchitectural footprints that attackers can expl
 oit. Previous work showed that instruction and data prefetchers on Intel\,
  AMD and Apple processors are prone to microarchitectural side-channel att
 acks. In this paper we investigate the data stride prefetcher in the \\tex
 tit{Xuantie C910} -- a server-grade RISC-V processor extensively deployed 
 in cloud environments. Furthermore\, we present the first microarchitectur
 al attack targeting a hardware prefetcher on a RISC-V processors. In that 
 regard\, we port StrideRE on RISC-V processors to reverse engineer its har
 dware prefetcher. Finally\, we provide two Proof-of-Concept (PoC) attacks:
  partial memory address disclosure and control flow leakage. We find that 
 both attacks are effective across privilege levels.
DTSTAMP:20260522T163158Z
LOCATION:Poster Island A
SUMMARY:RISCY Prefetchers - Mohamed Soliman
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/HZQQP9/
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