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UID:pretalx-eu-summit-2026-KBLECB@cfp.riscv-europe.org
DTSTART;TZID=CET:20260610T112000
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DESCRIPTION:Floating-point unit (FPU) verification is inherently challengin
 g due to IEEE-754 corner cases\, multiple rounding modes\, exception handl
 ing\, subnormal behavior\, and the large input space introduced by mixed p
 recision. The CORE-V Floating-Point Unit (CVFPU) released as open source\,
  provides a highly configurable multi-format implementation but lacks an i
 ndustrial-grade functional verification framework. This work addresses tha
 t gap by proposing a structured UVM-based verification strategy tailored t
 o its configurable architecture. The approach integrates a variable-precis
 ion C++ reference model\, directed and constrained-random stimulus\, asser
 tion-based checks\, and coverage-driven closure.
DTSTAMP:20260522T163115Z
LOCATION:Poster Island A
SUMMARY:Functional Verification Strategy of the CORE-V Floating-Point Unit 
 (CVFPU) for RISC-V cores - Ihsane Tahir
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/KBLECB/
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