Functional Verification Strategy of the CORE-V Floating-Point Unit (CVFPU) for RISC-V cores RISC-V Summit Europe 2026

Functional Verification Strategy of the CORE-V Floating-Point Unit (CVFPU) for RISC-V cores
.ical
2026-06-10 11:20–11:30, Poster Island A

Floating-point unit (FPU) verification is inherently challenging due to IEEE-754 corner cases, multiple rounding modes, exception handling, subnormal behavior, and the large input space introduced by mixed precision. The CORE-V Floating-Point Unit (CVFPU) released as open source, provides a highly configurable multi-format implementation but lacks an industrial-grade functional verification framework. This work addresses that gap by proposing a structured UVM-based verification strategy tailored to its configurable architecture. The approach integrates a variable-precision C++ reference model, directed and constrained-random stimulus, assertion-based checks, and coverage-driven closure.

Ihsane Tahir

Ihsane Tahir received a M.S. degree in embedded systems from Grenoble INP - Esisar, Valence, France, in 2020. She subsequently joined CEA LIST as a research engineer. She then joined the OpenHW Foundation in 2026 as a hardware verification engineer. Her works include functional verification, FPGA prototyping and digital design.

Functional Verification Strategy of the CORE-V Floating-Point Unit (CVFPU) for RISC-V cores .ical 2026-06-10 11:20–11:30, Poster Island A

Functional Verification Strategy of the CORE-V Floating-Point Unit (CVFPU) for RISC-V cores
.ical
2026-06-10 11:20–11:30, Poster Island A