2026-06-10 –, Poster Island B
Microarchitectural performance evaluation is an essential step in modern processor design and architecture exploration. However, developing a cycle-accurate simulator from scratch requires implementing both instruction semantics and detailed microarchitectural models, which significantly increases development complexity.
This work presents RISCV-Perf, a lightweight performance modeling framework designed to integrate with the Spike RISC-V functional simulator. The framework decouples functional execution from cycle-level timing simulation through a minimal instruction interface that captures key instruction attributes such as program counters, operand registers, and memory access information. By reusing the functional correctness provided by Spike, RISCV-Perf focuses solely on modeling microarchitectural timing behavior.
RISCV-Perf adopts an execution-driven simulation approach, enabling cycle-level modeling of superscalar out-of-order processors without generating execution traces. The timing model represents major microarchitectural components including an instruction flow model, register renaming mechanism, memory operation pipelines, and cache hierarchy interactions. In addition, the framework is implemented using a modular policy-based design, allowing architectural components such as branch predictors and cache policies to be easily replaced or extended.
Experimental evaluation using the MiBench benchmark suite on an RV64GC configuration demonstrates that RISCV-Perf can effectively generate performance insights such as CPI behavior and branch prediction miss rates across workloads. These results show that the framework provides a practical platform for workload characterization and microarchitectural policy exploration.
RISCV-Perf is a research framework designed to support microarchitectural performance exploration for RISC-V processors while maintaining tight integration with existing functional simulators. Unlike many trace-driven simulators that require generating and storing large instruction traces, RISCV-Perf follows an execution-driven approach by directly interfacing with the Spike functional simulator. This design avoids trace generation overhead and simplifies modeling of speculative execution behavior.
The framework introduces a lightweight instruction interface that extracts essential instruction information during execution and forwards it to the timing model through an instruction pool and instruction buffer. This mechanism decouples functional execution from timing simulation and enables superscalar modeling where multiple instructions can be processed per cycle.
The timing model approximates the structure of modern superscalar out-of-order processors, including register renaming, instruction scheduling, memory operation handling, and cache hierarchy interactions. The design follows a modular architecture that allows researchers to experiment with alternative microarchitectural policies, such as different branch predictors or cache replacement algorithms, without modifying the overall simulation framework.
RISCV-Perf aims to provide a practical and extensible platform for early-stage architecture exploration, workload analysis, and microarchitectural policy evaluation for RISC-V systems.
Tsung-Li Chen is a master’s student in the Department of Computer Science and Information Engineering at National Taiwan University of Science and Technology (NTUST). His research interests focus on computer architecture, microarchitectural performance modeling, and RISC-V processor design. His current work explores lightweight performance simulation frameworks for modern out-of-order processors by integrating timing models with functional simulators. Tsung-Li has been actively involved in RISC-V related research and previously presented work at the RISC-V Summit North America.