Reactive real-time systems rely on preemption and, by extension, context switching (CS) to schedule critical tasks. Short, frequent interrupt routines may use a disproportinally large ammount of time and energy for CS rather than core application functionality. Replicated register files (RRFs) are an established solution for fast CS, but area-intensive and poorly scalable. This abstract presents the heterogeneous interrupt architecture, a solution for targeted use of RRFs that maintains area-efficiency, and the parallel context stack (PCS), a novel RRF microarchitecture. The proposed concepts are evaluated with implementations in TSMC 22-nm and a periodic task case study. The implementation in a RISC-V microcontroller system demonstrates a 1.2% area overhead with no timing detriment for the PCS, while the case study demonstrates a reduction in clock cycles and retired instructions of up to 26% and 21%, respectively.