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UID:pretalx-eu-summit-2026-LP7WTL@cfp.riscv-europe.org
DTSTART;TZID=CET:20260611T104000
DTEND;TZID=CET:20260611T105000
DESCRIPTION:As High-Performance Computing (HPC) advances towards the Exasca
 le era\, energy efficiency has become the primary design constraint. In HP
 C systems\, the Floating-Point Unit (FPU) is instantiated in massive numbe
 rs to support parallel workloads\, that require huge number of floating po
 int computations. Consequently\, the FPU becomes a dominant consumer of dy
 namic power within the chip. This work presents an energy-optimized FPU fo
 r RISC-V Vector Processing Units. To address the inefficiencies of standar
 d unified FMA datapath\, we propose a Split-Path FMA micro- architecture t
 ailored for the RISC-V Vector specification. Our design integrates the phy
 sical separation of the arithmetic pipelines with vector-aware clock gatin
 g and operand isolation. Evaluated in a commercial 4nm technology at 2 GHz
 \, the optimized design demonstrates up to a 29% increase in energy effici
 ency for mixed-arithmetic workloads and a 7.8% performance speedup in vect
 or reduction-heavy kernels.
DTSTAMP:20260522T163115Z
LOCATION:Poster Island A
SUMMARY:Energy-Efficiency Optimization of a RISC-V Floating-Point Unit for 
 HPC-Oriented Architectures - Marco Crisologo
URL:https://cfp.riscv-europe.org/eu-summit-2026/talk/LP7WTL/
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