2026-06-10 –, Poster Island D
Advanced Interrupt Architecture (AIA) Incoming MSI Controller (IMSIC) is a message-signaled interrupt (MSI) solution designed for the RISC-V External interrupt. However, due to the lack of native support for Software-Interrupt, IPI was forced to mix with IMSIC interrupts. In large systems, inter-processor interrupts (IPIs) occur very frequently and in large numbers, far exceeding the number of device interrupts. To alleviate IPI pressure on the Network-on-Chip (NoC), an interrupt-forwarding router is typically designed. However, the requirement for 2048 interrupt sources in the AIA IMSIC consumes a significant amount of SRAM in the BITMAP design, increasing chip area and cost. To improve IPI doorbell efficiency, hardware logic for merge-and-absorption based on BITMAP also needs to be designed per-hart at the transmitter, but AIA IMSIC's large interrupt sources design makes this design expensive. Furthermore, IMSIC's IPI allows any MSI-capable device to forge an IPI by sending a specific interrupt number, causing unnecessary disruption. To bridge this gap, propose a Software MSI Controller (SMSIC) for AIA, an optional RISC-V hardware component tightly coupled to each hart. The idea of architecturally separating IPIs from external interrupts not only reduces the cost of improving IPI performance in large systems but also aligns with the original intent of the Software Interrupt design in the RISC-V Privileged Specification.
In a RISC-V system, Message Signaled Interrupt (MSI) is directed not just to a specific hart but to different domains within that hart, such as the machine or supervisor level, or the VM domain. So, SMSIC contains a separate interrupt file for each privilege level. The MSI write to the interrupt file would raise a software interrupt of that privilege level. When a hart also implements the H extension, its SMSIC has additional interrupt files for virtual harts, called guest interrupt files, which are similar to AIA IMSIC. The number of guest interrupt files an SMSIC has is determined by GEILEN, the number of supported guest external interrupts, as defined by the H extension, which is the same as AIA IMSIC. SMSIC reuses CSR_HGEIP to notify the hypervisor of the virtual machine, rather than introducing a new CSR, as in AIA IMSIC.
A Linux kernel developer focuses on the CPU subsystem, including virtualization, IOMMU, PCIe, Heterogeneous Programming, and RV64ILP32.
Staff Engineer, Alibaba Damo Academy