The surging demand for VM-based secure containers in the AI Agent era is driving rapid growth in the scale of vCPU deployments. However, the current RISC-V AIA specification co-locates inter-processor interrupts (IPIs) and device interrupts within the IMSIC, causing hardware resource overhead to scale multiplicatively with both the per-file size and the total count of S/VS-files — a structural coupling that fundamentally limits vCPU interrupt pass-through scalability.
To address this, we propose the Software-interrupt MSI Controller (SMSIC), an AIA extension that explicitly decouples IPI from the IMSIC external interrupt hierarchy and establishes a dedicated MSI delivery path for the software interrupts defined in the RISC-V privileged specification. By fully decoupling the IPI path from the device interrupt path, SMSIC reduces the per-VS-file IPI resource to a single interrupt entry, comprising only one enable bit and one pending bit, thereby supporting large-scale VS-file deployment at minimal hardware cost (for both the per-hart and SoC IPI merging & absorption components). Furthermore, with the IPI path isolated, IOMMU MRIF can scale the number of virtualization interrupt files to support larger-scale deployments of vCPU interrupt pass-through, effectively taking over the scalability role from native IMSIC VS-files.