We present Wolvrix, an open-source infrastructure that ingests Verilog-2005/SystemVerilog into GRH (Graph RTL Hierarchy), an SSA-based graph intermediate representation, and supports composable transformation passes with Verilog re-emission. Wolvrix models complex SystemVerilog semantics, including multi-event registers, multi-port memories, blackboxes, cross-module references, and DPI-C calls, within a uniform graph structure amenable to analysis and transformation. We describe GRH and Wolvrix's architecture, and present roundtrip re-emission on XiangShan and XuanTie C910 plus RepCut partitioning on XiangShan.